Fin Field-Effect Transistor and Method for Fabricating a Fin Field-Effect Transistor

ABSTRACT

A fin field-effect transistor has a substrate and a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain regions are formed once a gate has been produced.

This application is a continuation of U.S. patent application Ser. No.10/768,971, filed on Jan. 30, 2004, which is a continuation ofInternational Patent Application Serial No. PCT/DE02/02760, filed onJul. 26, 2002, which published in German on Feb. 20, 2003 as WO03/015182 A2, and which claimed priority to German Patent ApplicationNo. 101 37 217.5, filed on Jul. 30, 2001, all of which applications areincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a fin field-effect transistor and amethod for fabricating a fin field-effect transistor.

BACKGROUND

A fin field-effect transistor and a method for fabricating such a finfield-effect transistor are described in D. Hisamoto, et al., “A FullyDepleted Lean-Channel Transistor (DELTA)—A novel vertical ultrathin SOIMOSFET,” IEEE Electron Device Letters, Volume 11, No. 1, pages 36-38,1990 (hereinafter “Hisamoto 1990”). FIG. 2 shows such a fin field-effecttransistor 200 having a silicon substrate 201 and an oxide layer 202made of silicon oxide SiO₂ on the silicon substrate 201.

A fin 203 made of silicon is provided on a part of the oxide layer 202.A gate 204 of the resulting fin field-effect transistor 200 is arrangedabove a part of the fin 203 and along the entire height of the part ofthe fin 203.

In the case of the fin field-effect transistor 200 described in Hisamoto1990, the channel region, not visible in FIG. 2, of the fin 203 can beinverted by charge carriers with the aid of the gate 204 extending alongthe sidewalls 205 of the fin 203. The fin 203, which is also referred toas a Mesa, has on its end sections a source region 206 and a drainregion 207.

In the case of the fin field-effect transistor 200 described in Hisamoto1990, there is no self-aligned spacer technology for the LDDimplantation or HDD implantation, in order that the fin 203 is nothighly doped with doping atoms in the source region 206 and in the drainregion 207 until after the application of the gate 204, and that anoverlapping of the gate 204 and the source region 206 or the drainregion 207, and a disadvantageous control response, associated therewithin turn, of the fin field-effect transistor 200 is avoided.

In the case of the fin field-effect transistor 200 described in Hisamoto1990, there are firstly formed along the sidewalls 205 of the fin 203oxide spacers 208 which prevent a doping of the fin 203 by implantationvia the sidewalls 205. In the case of implantation via the free finsurfaces, however, in addition to the source region 206 and the drainregion 207, the channel region that is not protected by oxide spacers208 is provided with doping atoms. In the case of this underdiffusion,doping atoms pass laterally into the channel region after theirimplantation. Particularly in the case of short channel lengths—such asoccur in the case of the known fin field-effect transistor 200—suchunderdiffusion has substantial negative effects on the control responseof the fin field-effect transistor 200.

Furthermore, there is described in D. Hisamoto, et al., “AFolded-Channel MOSFET for Deep-Sub-Tenth Micron Era, IEDM 98, pages1032-1034, 1998 (hereinafter “Hisamoto 1998”) a fin field-effecttransistor in the case of which the silicon fin is fed through in thehorizontal direction by the electric current to be controlled. In thefabrication method in accordance with Hisamoto 1998, the highly dopedsource/drain regions are already present when the gate oxide made ofsilicon dioxide is grown on. This leads to a substantial running of thedopant and to undesired series resistances, particularly in the case ofa very short channel.

J. Kedzierski, et al., “Complementary Silicide Source/Drain Thin-BodyMOSFETs for the 20 nm Gate Length Regime,” IEDM 2000, pages 57-60,describes a MOS field-effect transistor in the case of which the drainregion and the source region are formed from platinum silicide.

U.S. Pat. No. 6,252,284 B1 describes a planarized fin field-effecttransistor in the case of which a spacer is arranged as electricalinsulation layer between source and gate and between drain and gate,respectively, in each case between source and gate and between drain andgate.

Furthermore, U.S. Pat. No. 5,300,455 describes a method for fabricatingan electrically conductive diffusion barrier at the metal/siliconinterface of a MOS field-effect transistor.

U.S. Pat. No. 6,207,511 B1 describes a transistor having one or morestrip channels and in the case of which the current flow takes place inthe lateral direction between source and drain. The gate is located atthe sidewalls and, if required, on the strip channel or channels.

U.S. Pat. No. 5,623,155 describes an SOI-MOS field-effect transistor.

U.S. Pat. No. 4,996,574 describes a MIS transistor structure forincreasing the conductivity between source and drain.

SUMMARY OF THE INVENTION

The present invention is based on the problem of specifying a finfield-effect transistor in which underdiffusion in the channel regionbelow the gate in the context of implantation with doping atoms isavoided, and in which running of doping atoms is avoided and seriesresistances caused thereby are prevented.

Furthermore, the present invention is based on the problem of specifyinga method for fabricating such a fin field-effect transistor.

The problems are solved by the fin field-effect transistor and by themethod for fabricating the fin field-effect transistor having thefeatures in accordance with the claims of the present application.

In the context of the present invention, a fin field-effect transistorshould generally be understood to mean a field-effect transistor whosechannel region is of fin-shaped construction and constructed in avertically projecting fashion—also in an uncovered manner, or above aninsulator layer, for example an oxide layer. The fin field-effecttransistor has a gate which extends partly above a vertically projectingstructure and along its sidewalls.

A fin field-effect transistor according to the present invention has asubstrate, a fin above the substrate, and also a drain region and asource region outside the fin above the substrate. In this case, the findoes not contain the source region and the drain region, as it does inknown fin field-effect transistor arrangements. The fin serves only as achannel between source region and drain region. A diffusion barrier isarranged in each case between the drain region and the fin and betweenthe source region and the fin.

A further fin field-effect transistor according to the presentinvention, which optionally has a diffusion barrier in the same way asthe previously described fin field-effect transistor, has a substrate, afin above the substrate, and a drain region and a source region outsidethe fin above the substrate with the fin serving as a channel betweenthe source region and the drain region.

The drain region and the source region are formed from a material withmetallic conductivity in electrical terms, a Schottky barrier beingformed between the drain region and the fin and between the sourceregion and the fin.

The material with metallic conductivity may be platinum silicide,platinum germanium silicide or erbium silicide. It is preferred to useplatinum silicide or platinum germanium silicide as material withmetallic conductivity in a p-channel MOS fin field-effect transistor,and erbium silicide as material with metallic conductivity in ann-channel MOS fin field-effect transistor.

In an exemplary method according to the present invention forfabricating a fin field-effect transistor, a fin is formed above asubstrate. A gate layer is formed at least above a part of the fin. Thearrangement thereby formed, if appropriate extended by a gate protectivelayer and a gate spacer according to one of the following advantageousdevelopments of the present invention, is coated with an insulationlayer. Subsequently, the insulation layer is removed in the region ofthe ends of the fin in such a way that at least a part of the two endsof the fin is uncovered. The regions uncovered from the insulation layerare filled at least partly with material for forming a source region anda drain region.

The present invention specifies for the first time a fin field-effecttransistor in the case of which the fabrication of the channel regionand the fabrication of the source and drain regions are performed in afashion uncoupled from one another. The associated fabrication methodscan also be optimized separately from one another.

In this case, the gate is fabricated above the channel before the sourceand drain regions are fabricated. This creates a self-alignedarrangement in the case of which the gate region cannot overlap with thesource region or the drain region and thus bring about undesiredcoupling capacitances.

Moreover, the running of doping atoms owing to the production, occurringafter the fabrication of the gate, of the highly doped source and drainregions is avoided in the case of the present invention, as a result ofwhich no undesired series resistances are formed.

Moreover, in the case of a fin field-effect transistor according to thepresent invention, the source region and the drain region of the finremain freely accessible, thereby enabling exact and simple doping ofthe source region and of the drain region of the fin.

Preferred developments of the invention emerge from the dependentclaims.

The refinements described below refer both to the fin field-effecttransistor and to methods for fabricating the fin field-effecttransistor.

The substrate may have silicon, and, as an alternative, it is alsopossible to provide on the substrate a further layer, for example madeof silicon oxide, generally made of an oxide on which the fin and alsothe gate are arranged.

In accordance with a refinement of the present invention, the gate haspolysilicon. Furthermore, the gate may also be formed by a stack ofpolysilicon and tungsten silicide.

The spacer may have silicon oxide and/or silicon nitride.

The drain region and/or the source region may have polysilicon.

The source region may be arranged at one end of the fin, and the drainregion may be arranged at the other end of the fin.

In a further advantageous development of the present invention, thesource region on one end face of the fin cooperates with the fin, andthe drain region on the other end face of the fin cooperates with thefin, the end faces terminating the fin in its longitudinal extent.

The source region can, however, also additionally cooperate with the finwith a part, not covered by a gate, of a broad side of the fin, and thedrain region can cooperate with the fin with a further part, not coveredby the gate, of a broad side of the fin, the broad sides connecting theend faces of the fin to one another. The area of the active connectionof source and drain to the channel is thereby increased. In this casethe source and drain regions can directly adjoin the fin.

In a further advantageous development of the present invention, thesource region cooperates with the fin exclusively at one end face of thefin, and the drain region cooperates with the fin exclusively at theother end face of the fin. This refinement is particularly advantageouswhenever the aim is to arrange one diffusion barrier each between drainregion and fin, and between source region and fin, which diffusionbarrier is intended to prevent indiffusion of the dopant for the sourceand drain.

A gate and a spacer can be arranged at least above a part of the fin andin this case extend essentially along the entire height of the part ofthe fin. The gate layer can be arranged between spacers in this case.The gate layer can also be covered by a protective layer. If, moreover,an oxide layer and/or a nitride layer are/is provided between the finand gate layer relative to the underside of the gate layer, the gate isencapsulated. The encapsulation components preferably have silicon oxideor silicon nitride. In this case, it is also possible to use bothmaterials in layers so that one material can be etched selectivelyrelative to the other, simplified fabrication methods thereby beingpossible. It is to be noted in this context that this describedencapsulation can also advantageously be provided in the case of a finfield effect transistor in which the diffusion barriers are notprovided.

The gate and/or the spacers may extend essentially along the entireheight of the part of the fin. Furthermore, the height of the spacerwith respect to the substrate may be essentially equal to the height ofthe gate.

Underdiffusion during implantation of the source region and the drainregion of the fin field-effect transistor is practically completelyavoided by virtue of this refinement.

The gate including the edge-side spacers can extend along the entirelength of the fin, the spacers terminating flush with the end faces ofthe fin, that is to say the outer sides of these edge-side spacers liein one plane with the end faces of the fin. In the case of thisadvantageous development, it is then only the end faces of the fin thatare freely accessible to coupling with the subsequently inserted sourceand drain regions, it being possible here to provide the dielectricbarriers, with their previously described advantages, in a particularlysimple way.

The subsequently deposited drain and source regions can have a smallerheight above the substrate surface than the insulating region. As aresult, there is no need for the uncovered regions in the insulationlayer to be filled up completely, and so the design height of theoverall arrangement can be kept small.

In order to form the fin of the fin field-effect transistor, it ispossible to apply a mask marking a fin on one silicon layer of asubstrate of two silicon layers enclosing a basic oxide layer. Thesilicon material of this layer is removed in such a way that a siliconbody in the form of the fin is formed on the insulation layer. Thehard-surface mask may in this case contain silicon oxide and/or siliconnitride.

The gate can be formed by the temporarily sequential application of agate layer, the application of a protective layer to the gate layer, theapplication of a mask for the further structuring of the gate, and theremoval of excess material of the gate and protective layers, in such away that a strip-shaped stack, laid over the fin, made from a gate layerand a protective layer is formed.

Spacers may be formed in the following steps: coating the arrangementwith a spacer layer, and removing the spacer layer in such a way thatthe further spacer layer forms spacers at least on the sides of the gatethat are still uncovered before the coating with the spacer layer. Thespacer layer and/or the protective layer may contain silicon nitride.

If a diffusion barrier is provided, this is performed—preferably at eachuncovered end face of the fin—after the application of the insulationlayer and of the at least partial uncovering of the ends of the fin.

Source and drain regions are produced by virtue of the fact that theprevious arrangement of fin, gate and, if appropriate, spacers andprotective layer is coated with an insulation layer, which is thenremoved again in the region of the ends of the fin after a maskingoperation marking the regions to be uncovered. These uncovered regionsare then filled with a material which is already doped, or is dopedafter the deposition.

At least some of the elements of the fin field-effect transistor may beformed by means of deposition. Thus, in accordance with thisdevelopment, it is possible to use a conventional semiconductorprocessing technique, thus enabling the fabrication method to beimplemented in a simple and cost-effective way.

However, in addition to CVD methods it is also possible to usesputtering or vapor deposition methods to arrange layers or materials inthe proposed application process.

Exemplary embodiments of the present invention are illustrated in thefigures and are explained in more detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a longitudinal section of an exemplary embodiment of a finfield-effect transistor in accordance with the present invention;

FIG. 2 shows an oblique view of a fin field-effect transistor inaccordance with the prior art;

FIG. 3, which includes FIGS. 3 a to 3 f, shows sectional views of a finfield-effect transistor illustrating the individual method steps of amethod for fabricating the fin field-effect transistor of FIG. 1; FIGS.3 a, 3 b, 3 d and 3 f show, however, the top view, belonging to thecross section, of the fin field-effect transistor in the respectivemethod step;

FIG. 4 shows a top view of the geometry of masks used in fabricating thefin field-effect transistor according to FIGS. 1 and 3; and

FIG. 5 shows a longitudinal section of a further exemplary embodiment ofa fin field-effect transistor according to the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1 shows a fin field-effect transistor 100 in accordance with anexemplary embodiment of the present invention, in longitudinal section.The section is carried out in this case longitudinally through the finof the fin field-effect transistor, approximately along the section lineA-A′, to be seen in FIG. 2, in the middle of the fin, FIG. 2 being usedin this context merely to explain the position of the section line withreference to the fin. Otherwise, however, the longitudinal sectionaccording to FIG. 1 is a longitudinal section through a fin field-effecttransistor according to the present invention, but the fin field-effecttransistor according to FIG. 2 is a known fin field-effect transistorwhose longitudinal section differs substantially from the longitudinalsection according to FIG. 1.

The fin field effect transistor 100 has a substrate 101, on which anoxide layer 102 made of silicon oxide SiO₂ having a layer thickness ofapproximately 200 nm is arranged (compare FIG. 1).

A fin 103 made of silicon is formed on the oxide layer 102. Spacers108—preferably made of silicon nitride Si₃N₄—and a gate 104 made ofpolysilicon are arranged between the spacers 108 above a subregion ofthe fin 103. The gate layer may also have p+-doped SiGe.

A nitride layer 114—preferably made of silicon nitride Si₃N₄—and anoxide layer 113—preferably made of silicon oxide SiO₂—lie arranged oneabove another between the gate 104 and the spacers 108, on the one hand,and the fin 103, on the other hand. The nitride layer 114 is used inorder to ensure that the gate oxidization is performed only on thesidewalls of the gate 104. The oxide layer 113 serves as a hard-surfacemask.

A protective layer 107 made of silicon nitride Si₃N₄ for protecting thegate 104 is applied above the gate 104. In addition—which cannot be seenin the longitudinal section in accordance with FIG. 1—the gatearrangement 104, 107, 108 also extends, along its width at the fin 103,in the vertical direction along the broad sides of the fin 103 and inthe corresponding, linearly continued region on the oxide layer 102above the substrate 101 into the plane of the drawing and out of theplane of the drawing.

A source region 109 and a drain region 110 of the fin field-effecttransistor 100 are arranged adjacent to the ends of the fin 103 and inthis case on the end faces 105 of the fin 103.

Source region 109, drain region 110, fin 103 and gate arrangement 104,107, 108 are arranged in this case in a cut-out of an insulation layer115.

Insulation layer 115, gate arrangement 104, 107, 108 and partially alsosource region 109 and drain region 110 are coated by a furtherprotective layer 111.

Contacts 112 made of metal, preferably aluminum, serve to make electriccontact with source region 109 and drain region 110.

Source region 109 and drain region 110 are therefore coupled to oneanother in a conducting fashion as a channel region via the fin 103 as afunction of the control by means of the gate 104.

Hereinafter, the same reference symbols are used for identical elementsin different drawings.

The individual method steps for fabricating the fin field-effecttransistor 100 in accordance with the first exemplary embodiment inlongitudinal section are explained below with reference to FIG. 3 a toFIG. 3 f. To improve the illustration, the associated top view of thefin field-effect transistor undergoing fabrication is also specified inthis case in some sectional views characterizing method steps.

The fin field-effect transistor 100 is designed as an SOI structure(SOI: Silicon on Insulator). In this case, the structure is constructedon the insulation layer of a wafer.

The starting point is an SOI wafer, that is to say clearly a siliconsubstrate 101 in which a basic oxide layer 102 made of silicon oxideSiO₂—also termed buried oxide—is situated interposed in the manner of asandwich (compare FIG. 3 a). In FIG. 3 a, there is already remaining onthe basic oxide layer 102 only a fin 103 which has been structured fromthe originally present silicon layer.

In order to fabricate the fin 103, a hard-surface mask made of a nitridelayer made of silicon nitride Si₃N₄ and of an oxide layer, lying thereabove, made of silicon oxide SiO₂ is applied to the silicon layer. Thismask serves for fabricating the fin 103.

The geometrical design of this mask M1 is to be seen in top view fromFIG. 4. The excess material is subsequently removed from around thehard-surface mask, preferably by means of reactive ion etching afterelectron beam lithography has been performed, such that the structure ofthe fin 103 on the basic oxide layer is maintained (see FIG. 3 a).

It is thereby possible subsequently to apply photoresist to the siliconlayer formed, and the silicon which is not covered with photoresist canbe etched by means of a dry etching method. The etching method isstopped as soon as the surface of the basic oxide layer 102 is reached.

The top view in FIG. 3 a shows the fin 103 on the basic oxide layer 102,to which the shape of the mask M1 from FIG. 4 corresponds in top view.

It is subsequently possible as an option to set the threshold voltage ofthe fin field-effect transistor 100 by implanting doping atoms, forexample boron atoms, into the fin 103. In the case of a completelydepleted transistor, this channeled implantation can also be omitted inthe course of the method.

In further steps, the gate 104 is formed by gate oxidation and aprotective layer is formed. For this purpose, a gate layer made ofpolysilicon and a protective layer made of silicon nitride Si₃N₄ aredeposited onto the arrangement according to FIG. 3 a by means of a CVDmethod. During the deposition of the polysilicon, the resultingpolysilicon layer is doped with phosphor atoms or boron atoms (in situdoped deposition).

Subsequently, a mask is applied to the protective layer in order to forma strip-shaped stack structure of gate and protective layers. Thegeometrical shape of a mask in top view is shown by the mask M2 fromFIG. 4. Excess material is removed after the application of the mask M2with the aid of a suitable structuring method. For example, photoresistis applied to the silicon nitride protective layer 107 in such a waythat the region which is intended to be used later as gate 104 is notetched through the photoresist in further etching steps. In a subsequentstep, the silicon nitride protective layer 107 is then etched by meansof a dry etching method, as also is the polysilicon layer 106, formingthe gate, which is not covered with photoresist.

The etching method is terminated above the fin 103 on the oxide layer113 and above the substrate 101 on the surface of the basic oxide layer102, such that oxide is not etched.

The photoresist is subsequently removed from the silicon nitride layer107.

After these method steps, a strip-shaped stack of gate 104 andprotective layer 107 is arranged above the fin 103 and a part of thesubstrate 101 according to FIG. 3 b.

Illustrated in the top view according to FIG. 3 b is the protectivelayer strip 107 below which the gate strip 104 is situated. The striparrangement is partially guided over the fin 103.

At one end of the strip, the latter is of widened design in order tocreate a suitable surface for later applying a gate contact via. Thestrip shaped stack corresponds in top view in this case once againapproximately to the geometrical shape of the mask M2 from FIG. 4.

Spacers are formed on both sides of the uncovered edges of the gate in afurther step. For this purpose, the arrangement according to FIG. 3 b iscoated with a spacer layer 108 (see FIG. 3 c). The coating is performedby means of a conformal CVD deposition. In this case, the spacer layer108 contains silicon nitride Si₃N₄.

The spacers 108 lying on the edge sides of the gate 104 are produced byanisotropic back etching of the silicon nitride spacer layer 108 withstrong overetching. Spacers on the channel fin 103 are removed by theoveretching. It is possible to determine, by varying the width of thespacers 108, to what extent the source and drain regions 109, 110 laterproduced cooperate with the channel.

FIG. 3 d shows the arrangement after these fabrication steps. The gate104 is encapsulated in this case in a structure of spacers 108 and theprotective layer 107. Moreover, FIG. 3 d shows once again the top viewof the arrangement after the abovementioned fabrication steps. The term“encapsulated” is to be understood in this context in such a way thatthe gate 104 is fully covered by the spacers 108 on its side faces, andon the upper surface of the gate 104 by the protective layer 107, suchthat no surface areas of the gate 104 are uncovered anymore.

Subsequently, an insulation layer 115 made of silicon oxide SiO₂ isdeposited onto the arrangement according to FIG. 3 d by means of a CVDmethod.

Subsequently, a part of the silicon oxide insulation layer 115 isremoved again by means of a chemical mechanical polishing method untilthe silicon nitride protective layer 107 is reached. The CMP method isstopped once the silicon nitride protective layer 107 is reached.

The arrangement according to this fabrication step is shown inlongitudinal section in FIG. 3 e.

Subsequently, a mask is arranged on the insulation layer 115, forexample in the form of photoresist. The geometrical shape of this maskis reproduced in top view by the mask M3 from FIG. 4.

Subsequently, a dry etching method is used to etch silicon oxide fromthe insulation layer 115 down to the surface of the basic oxide layer102. The dry etching is selective with respect to silicon nitride, suchthat the etching process is stopped at the nitride layer 114 in theregion of the fin 103, and the nitride-containing spacers 108 andprotective layer 107 are not etched away in the region of the gatearrangement.

In accordance with FIG. 3 f, the ends of the fin 103 are freelyaccessible after this fabrication step. This is necessary in order toconnect the fin 103 serving as a channel to a source region and a drainregion.

The accesses/holes, uncovered by the preceding etching operation, to thefin ends are filled at least partially with suitable material,preferably polysilicon, in order to form a source region and a drainregion, a thin dielectric layer, forming a diffusion barrier, previouslybeing applied to the uncovered accesses/holes to the fin ends, which areintended to prevent diffusion of doping atoms from the source and draininto the channel region. The polysilicon is applied to the diffusionbarrier layer.

During the filling of the accesses with polysilicon, the resultingpolysilicon layer is doped with suitable doping atoms (in-situ-dopedfilling). However, the polysilicon can also be applied by selectiveepitaxy or by CVD deposition with a subsequent CMP method and/orsuitable back etching.

As an alternative to the in-situ doping, the doping of the source region109 and the drain region 110 can also be performed by subsequentn+-implantation.

In any case, the production of the source and drain regions 109, 110 isperformed after the construction of the gate 104 above the fin 103, andso a field-effect transistor of self-adjusted design is created in thecase of which gate region and source or drain regions do not overlap andinfluence one another disadvantageously.

An undesired implantation of atoms into the channel region is alsoavoided with this fabrication method.

FIG. 3 f shows an arrangement after carrying out these fabrication stepsin longitudinal section and in top view.

In final standard semiconductor process steps, siliciding takes placeand produces a silicide layer on the source and drain regions 109, 110for the purpose of reducing the contact resistance to contacts, still tobe fitted, for source, gate and drain. Tungsten serves as actual contactmaterial. Serving in this case as an adhesion layer and a diffusionbarrier therefor is a double layer made of titanium and titanium nitridewhich is sputtered onto the source region 109 and the drain region 110.Only then is contact made with the gate, source and drain.

The contact vias are once again obtained with the aid of etchingprocesses. Firstly, a further protective layer 111 is deposited usingthe CVD method onto the existing arrangement for this purpose.Subsequently, a mask is applied, for example in the form of photoresist,to the further protective layer 111. The geometrical shape of this maskis shown by the mask M4 in FIG. 4, in top view. The mask M4 in this casemarks the regions provided for making contact with the gate, source anddrain.

Subsequently, regions are etched from the further protective layer 111by means of a dry etching method so as to create access to the source,drain and gate regions which is free and direct or indirect via thesilicide layer. These accesses are then filled with metal-containingmaterial in order to form contacts 112.

A fin field-effect transistor according to the present invention isshown in FIG. 1 after these fabrication steps have been carried out.

FIG. 5 shows a second exemplary embodiment of a fin field-effecttransistor according to the present invention, in longitudinal section.

This fin field-effect transistor differs from the fin field-effecttransistor in accordance with FIG. 1 and FIG. 3 in that the width of thegate 104 including the spacers 108 corresponds to the length of the fin103.

The result of this, firstly, is that the source region 109 and the drainregion 110 can cooperate with the fin 103 only on the end faces 105thereof. The outer sides of the spacers 108 lie in a plane with the endfaces 105 of the fin 103. By contrast, in the case of the exemplaryembodiment according to FIG. 1 and FIG. 3, the source region 109 and thedrain region 110 can also cooperate with end regions 105 of broad sidesof the fin 103, the broad sides of the fin 103 projecting from the basicoxide layer 102 and connecting the end faces 105 of the fin 103 to oneanother.

In the exemplary embodiments shown, the cooperation of source and drainregions 109, 110 with the fin 103 serving as a channel can be ensured byvirtue of the fact that source and drain regions 109, 110 bear againstthe sides provided for the purpose on the fin 103.

In the exemplary embodiment according to FIG. 5, however, there are setup according to the present invention between the end faces 105 of thefin 103 and the source region 109 and the drain region 110 diffusionbarriers 106 which are intended to prevent diffusion of doping atomsfrom the source and drain into the channel region.

In an advantageous way, these diffusion barriers are produced after thegate arrangement 104, 107, 108 has been produced, and the ends of thefin 103 have been uncovered again after the deposition of the protectivelayer 115, and before these uncovered regions are once again filled withmaterial in order to form source and drain. The diffusion barriers areproduced in this case by thermal oxidation.

1. An integrated circuit comprising: an insulating layer; a firstsource/drain portion and a second source/drain portion; and a channeldisposed between the first and second source/drain portions, wherein thechannel is disposed in a fin disposed over the insulating layer, andwherein an upper surface of the first and second source/drain portionsis disposed at a higher height than an upper surface of the channel, theheight being measured with respect to an upper surface of the insulatinglayer.
 2. The integrated circuit of claim 1, wherein at least one of thefirst and second source/drain portions comprises polysilicon.
 3. Theintegrated circuit of claim 1, wherein at least one of the first andsecond source/drain portions comprises a silicide containing a metal. 4.The integrated circuit of claim 1, wherein the fin includes silicon. 5.The integrated circuit of claim 1, further comprising a substratebeneath the insulating layer.
 6. An integrated circuit comprising: aninsulating layer; a first source/drain portion and a second source/drainportion; a channel disposed between the first and second source/drainportions; a gate electrode adjacent the channel; and an intermediatelayer disposed between the channel and the first and second source/drainportions, respectively, wherein the channel is disposed in a findisposed over the insulating layer, and wherein the first and secondsource/drain portions are self-aligned with respect to the gateelectrode.
 7. The integrated circuit of claim 6, wherein at least one ofthe first and second source/drain portions comprises polysilicon.
 8. Theintegrated circuit of claim 6, wherein at least one of the first andsecond source/drain portions comprises a silicide containing a metal. 9.The integrated circuit of claim 6, wherein the fin includes silicon. 10.An integrated circuit comprising: an insulating layer; a firstsource/drain portion and a second source/drain portion; and a channeldisposed between the first and second source/drain portions, wherein thechannel is disposed in a fin disposed over the insulating layer, andwherein a width of the first or second source/drain portion is largerthan a width of the fin, the widths being measured perpendicularly withrespect to a line connecting the first and second source/drain portions.11. The integrated circuit of claim 10, further comprising anintermediate layer disposed between the channel and the first and secondsource/drain portions, respectively.
 12. The integrated circuit of claim10, wherein at least one of the first and second source/drain portionscomprises polysilicon.
 13. The integrated circuit of claim 10, whereinat least one of the first and second source/drain portions comprises asilicide containing a metal.
 14. The integrated circuit of claim 10,wherein the fin includes silicon.
 15. An integrated circuit comprising:an insulator layer; a fin disposed over the insulator layer; a firstsource/drain region and a second source/drain region disposed outsidethe fin over the insulator layer, the first and/or second source/drainregion being formed from a material with metallic conductivity; aSchottky barrier disposed between the first source/drain region and thefin and between the second source/drain region and the fin; and a gatedisposed adjacent a channel portion of the fin, the channel portionproviding a current path between the first source/drain region and thesecond source/drain region.
 16. The integrated circuit of claim 15,further comprising a diffusion barrier disposed between the firstsource/drain region and the fin and between the second source/drainregion and the fin.
 17. The integrated circuit of claim 15, wherein thegate extends substantially along the entire height of at least a part ofthe fin.
 18. The integrated circuit of claim 15, further comprising asubstrate, wherein the insulator layer overlies the substrate.
 19. Theintegrated circuit of claim 15, wherein the material with metallicconductivity comprises a silicide.
 20. The integrated circuit of claim19, wherein the material with metallic conductivity comprises a materialselected from the group consisting of platinum silicide, platinumgermanium silicide and erbium silicide.